1. Field of the Invention
The present invention relates generally to amplifier circuits and in particular to amplifiers having frequency compensation which permits the amplifier to remain stable while driving heavy and light loads.
2. Description of Related Art
There is an increasing demand for low cost voltage regulators having low drop out (LDO) voltage capabilities for use as a power source in battery-powered equipment and the like. FIG. 1 is a simplified schematic diagram of a conventional CMOS LDO regulator. The regulator is powered by a power source, such as a battery, which provides an input voltage Vin. A transconductance amplifier Ga is provided having a non-inverting input connected to a reference voltage Vbg typically provided by a band gap voltage reference circuit. A transconductance amplifier is typically characterized as requiring very little current, having a relatively high output impedance and having external frequency compensation.
The output of amplifier Ga is connected to the gate of a P channel PET MA which functions as the series pass element of the regulator. The source and body of transistor MA are both connected to the input voltage Vin, with the drain connected to the regulator output where output voltage Vout is produced. Resistors RA and RB are connected in series between the output of the regulator and the circuit common. The node intermediate resistors RA and RB is fed back to the non-inverting input of amplifier GA. In that transistor MA operates to invert the output of amplifier GA, the feedback path is an overall negative path such that the non-inverting input of amplifier GA is maintained at essentially the same voltage as the inverting input, namely, voltage Vbg. Thus, the voltage at the node intermediate resistors RA and RB is at voltage Vbg. Thus, the current flow through resistor RB is equal to Vbg/RB, this being the same current as through resistor RA. Thus, the voltage drop across resistor RA is equal to the RB(Vbg/RA). Voltage Vout is equal to the sum of the two voltages as follows:                     Vout        =                  Vbg          ⁡                      (                          1              +                              RA                RB                                      )                                              (        1        )            
In R.F. applications, Vout is typically +2.8 volts.
The FIG. 1 circuit produces two poles PA and PB and a single zero ZA. The first pole PA is as follows:                     PA        =                  1                      (                          2              ⁢              π              ⁢                              xe2x80x83                            ⁢              RloadCload                        )                                              (        2        )            
The second pole PB is a function of the output impedance Rout of amplifier GA and the gate capacitance Cgate of transistor MA as follows:                     PB        =                  1                      (                          2              ⁢              π              ⁢                              xe2x80x83                            ⁢              RoutCgate                        )                                              (        3        )            
The zero ZA is a function of the equivalent series resistance Resr of the load capacitor and the capacitance Cload of the load capacitor and is as follows:                     ZA        =                  1                      (                          2              ⁢              π              ⁢                              xe2x80x83                            ⁢              Re              ⁢                              xe2x80x83                            ⁢              srCload                        )                                              (        4        )            
FIG. 2 is a frequency response diagram showing the relative locations of the poles PA and PB and zero ZA. The location of pole PA is a function of the load, as can be seen by equation (2) and will tend to move to a lower frequency under light load conditions (Rload becomes larger) and towards a higher frequency under heavy load conditions. As can be seen from equation (4), the location of zero ZA will move towards a lower frequency for larger values of the equivalent resistance Resr. Pole PA is determined by amplifier GA and transistor MA as can be seen by equation (2) and thus does not shift with changes in the load. Under light load conditions, when Rload is large, pole PA, sometimes referred to as the load pole, will move towards fixed pole PB. The two poles will combine to create a phase shift which will reduce the stability of the circuit under light load conditions. The phase shift is offset by the presence of zero ZA which thereby tends to maintain stability. However, in order to locate zero ZA near fixed pole PB, the value of Resr must be maintained at a relatively high value. Unfortunately, resort must be made to expensive tantalum capacitors having high values of Resr in order to force the zero ZA to be located at the desired low frequency.
A buffer stage has been added to prior art circuits, intermediate the amplifier Ga output, and output transistor MA. This operates to reduce effective the output impedance of the transconductance amplifier so that pole PB will be shifted to a higher frequency as indicated by equation (3) above. This eliminates the no/low load instability problems previously noted. However, under heavy load conditions load pole PA will shift upwards in frequency and approach pole PB. This will again produce instability problems.